YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
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PicoRV32 - A Size-Optimized RISC-V CPU
The USRP™ Hardware Driver Repository
Raptor end-to-end FPGA Compiler and GUI
HDL libraries and projects
Verilog AXI components for FPGA implementation
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
Verilog Ethernet components for FPGA implementation
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
SystemVerilog support for Yosys
Verilog UART
Must-have verilog systemverilog modules
The Ultra-Low Power RISC-V Core